FEDC provides comprehensive flexible electronics capabilities that bridge the high risk, resource intensive gap between innovation and product development in an information-secure environment. Backplane electronics design, fabrication, test and integration capability are all located within the FEDC headquarters at ASU Research Park in Tempe. The center operates dedicated pilot line toolsets for technology development and for technology demonstrator production. The 6” wafer-scale Pilot Line tools are dedicated to R&D starts and support of the GEN II line including process development and improvement for advanced technology insertion. The GEN II 370 x 470 mm display-scale pilot line tools are dedicated to low-volume manufacturing.
- Integrated circuit (IC) design and development and fabrication of inorganic and organic thin film transistor (TFT) arrays
- Design for manufacturability with high yield and optimal circuit performance
- Early stage prototyping and low-volume production