
Capabilities
Highlights
- ASU Research Park, Tempe, AZ location
- State-of-the-art infrastructure
- Structural design accommodates large display tools and equipment
- 250,000 sq. ft. total capacity
- 25,000 sq. ft. Class 10/100/1000 clean room
- R&D, pilot line and production capable
- 12,000 sq. ft. wet/dry labs Class 10,000 and non-rated
- Substantial H6 capability
- Flexible subdivision provides secure space for proprietary programs
Pilot line tools
Pilot line fabrication capabilities:
- 6-In. (150 mm) Wafer-scale Pilot Line for Research and Development (3 micron feature size (L/S))
- GEN II (370 mm x 470 mm) Pilot Line for Low Volume Production (3 micron feature size (L/S))
Both Pilot Lines are linked to a Manufacturing Execution System (MES) for Efficient Lot Management and Statistical Process Control (SPC), providing real time integrated information on:
- Lot status
- Quality
- Operational capability
The 6” wafer-scale and GEN II Pilot Line toolsets summarized in Table 1 with their associated fab processes, are fully consistent to enable straightforward scale-up. A comprehensive characterization and metrology toolset listed in Table 2 has been acquired to provide QA/QC, failure analysis and process improvement tools.
- Substrate / Planarization Material Systems: Si, Glass, PEN, Stainless Steel (SS), Polyimide
- Temporary Bonding Adhesives: 200ºC, 350 ºC
- Photolithography: GEN II Scale Automated Distortion Compensation for Plastic Substrate Materials (PEN),
- Deposition:
- Physical (sputter) vapor deposition (PVD): Al, Mo, ITO, Ta, IGZO
- Plasma-enhanced chemical vapor deposition (PECVD): a-Si, n+a-Si, p +a-Si, SiN, SiO2, SiON
- Etch: dry and wet
Leasing opportunities
- Class 10, class 100 and class 1,000 clean room space with/without sub fab
- Wet/dry lab space
Leasing information
Karen Honeycutt
Real Estate Operations Director
Phone: (480) 965-6700
Table 1: Pilot line toolset
PROCESS CELL | 6” WAFER CELL | GEN II 370X470MM |
---|---|---|
Clean | PCT | Universal Plastics |
Coat-Develop | Rite Track Series 8600 and 8800 | EVG 150 XL(s) and nTact Advantage II |
Photo Exposure | Canon MPA 600 | Azores 5200gT and Tamarack 304 |
PECVD | AMAT P5000 – MKII | AKT 1600 5-Chamber Cluster Tool |
Dry Etch a-Si | Tegal 903, AMAT 8330 | AKT 1600 5-Chamber Cluster Tool |
Dry Etch Nitride | Tegal 901 | AKT 1600 5-Chamber Cluster Tool |
Etch ITO | AMAT 8330 | AKT 1600 5-Chamber Cluster Tool |
Dry Etch Polymer | Tegal 901 | AKT 1600 5-Chamber Cluster Tool |
Plasma Strip | Gasonics L3510 | Etched in Time |
Sputter | 2-MRC 603 KDF 744 Sunic | KDF 744, Sunic |
Wet Etch | SPS | Universal Plastics |
Wet Resist Strip | Sage Solvent Hood | Foresight Engineering |
Bonding | Laurrel W6XX Coaters Western Magnum Laminators | DEK ELA Screen Printer Sun-Tec Laminator |
De-bonding | Custom Built Equipment | Custom Built Equipment |
MES | Mass Group | Mass Group |
Table 2: In-fab metrology tools
FUNCTION | TOOL SUPPLIER/MODEL | SCALE |
---|---|---|
TFT Autoprobe | Custom FDC | GEN II |
Automated Optical Inspection | Orbotech 7095 | GEN II+6 in |
Optical Microscopy / Critical Dimensions | Olympus Microscopes (2) | GEN II |
Film Stress | Flexus 2350 FP | GEN II |
Composition (N, H in a-Si:H and a-SiNx:H) | Thermoelectron FTIR | 6 in+ |
Film Thickness (transparent films) | Woollam Ellipsometer | GEN II |
Critical Dimensions / Profiles | JEOL FESEM 6300F | 6 in |
Particle Count | KLA Tencor 6100 | 6 in |
Surface Profiling / Roughness | Veeco SP3000W Interferometer Park 150 AFM | 6 in+ 6 in |
3 – Panel Probers 6 – Wafer Probers 1 – TNP Laser Repair | Custom FDC Electroglas Custom FDC | Gen II 6 in Gen II |
Film Thickness Profile / Step Height | Toho FP-10 KLA/Tencor P16+ | Gen II 6 in |
Substrate Flatness | FWB Custom FDC Tamar Technologies WaferScan | Gen II 6 in |
Resistivity-Rs | 4D 4-pt Probe | 6 in |
UV-IR Transmission | Cary UV-Vis | 6 in |
FEDC technologies
Electronic Design Automation (EDA) for IC Design, Modeling and Simulation:
- Professional suite of flexible/large area microelectronics design tools:
- Circuit simulation
- Design rule checking (DRC)
- Layer verification (LVS)
- Layout
- AutoPlace and route with standard cell library development capability
- State-of-the-art a-Si:H transistor models including VT Shift
- Extensive suite of digital and analog circuit testing equipment