General Dynamics C4 Systems demonstrated their Mission Briefer Technology Demonstrator using an Electrophoretic Display (EPD) fabricated by the FDC, at the Association of the United States Army (AUSA) Annual Meeting and Exposition. The EPD is made with electrophoretic front plane laminate developed by E Ink using backplane fabrication processes summarized below.
“Worlds first” demonstration of the use of integrated a-Si:H column drivers to drive an active matrix Electrophoretic Display (EPD) device. The a-Si:H column drivers and active matrix TFTs were fabricated using the FDC low-temperature flexible-substrate-compatible process. The EPD frontplane laminate was provided by E Ink. Click here for video.
The Natick Soldier Research, Development and Engineering Center (NSRDEC) and Army Research Labs (ARL) - Human Research and Engineering Directorate (HRED) conducted an evaluation of the Future Force Warrior (FFW) Soldier Flex PDA at the C4ISR ON THE MOVE (OTM) Event. The Soldier Flex PDA integrated a flexible display from the FDC with InHand Electronics Battery Smart software to create a rugged, low-power, ergonomic information device for the soldier. Infantry soldiers participated in a human factors study on the mechanical design and readability of the PDA. The PDA is to be used by the FFW rifleman to display maps, tracking information, memory joggers and for transmitting short text messages for mission planning during combat operations.
Hewlett Packard Company, one of the world’s largest IT companies became an Associate Member of the FDC.
Honeywell announced their launch of new materials developed in collaboration with the FDC through a project funded by the US Display Consortium. These materials are aimed at reducing manufacturing costs and power consumption while improving color uniformity and device lifespan for flat panel displays. The new materials are specifically focused on overcoming the challenges of planarization critical to flexible display development.
Shawn O’Rourke, FDC’s Director of Operations was awarded the 2007 Innovator of Tomorrow Award by Arizona Science and Technology Enterprises (AzTE) and ASU for developing promising intellectual property related to processing flexible displays. AzTE is an organization that licenses ASU’s intellectual property.
Click on either image to view video.
A flexible (de-bonded) SS 3.8-in. QVGA EP Display was demonstrated. This demonstration was enabled by successful solvent-release manual de-bonding; panel integration was performed after debonding. FDC technologies integrated in this demonstration include Honeywell planarization material and National Starch temporary bonding adhesive.
America's first flexible 4-in. diagonal active matrix (AM) QVGA reflective electrophoretic display (EPD) with a 
high performance low temperature a-Si:H active matrix transistor array directly fabricated on plastic. The array was fabricated with FDC’s 180 ° C process on DuPont Teijin Film’s heat-stabilized PEN.
Click image to view video.
Cosmetically perfect, high performance 4-in. diagonal AM QVGA reflective EPD produced on a rigid substrate (silicon). The array was fabricated with FDC’s 180°C a-Si:H process designed to be compatible with low temperature flexible substrates.
Test time for a complete 320 x 240 QVGA array automated electrical test was dramatically reduced from 5.5 hours to 65 minutes. Our full array test throughput capability is now on the order of two full lots (twelve wafers per lot, one array per wafer) in a 24-hour day, or over 1,500,000 transistors per day. A drive current array test map and corresponding display (a-Si on Silicon) are shown to the right.
Installation and functional testing of the entire FDC GEN II Display-scale (370 x 470 mm) Pilot Line completed one year ahead of our originally proposed schedule.
The AKT Deposition and Etch Tool shown to the right was custom-developed with FDC and includes a new substrate chuck design for high accuracy temperature control independent of plasma power.
The final tool installed was our Etched in Time (EIT) Oxygen Asher/Etcher for organic materials removal and patterning (shown to the left).
In collaboration with Kent Displays, fabricated a functional 64 x 64 chLC concept device that incorporated a novel AM pixel design. This novel design took advantage of recent improvements in Kent’s materials.
Unprecedented demonstration of a 35 µm wide metallic inkjet printed line on flexible Kapton and planarized PEN. Printing is of inter-digitated S/D electrodes for OTFTs using silver nanoparticles. Line spacing is about 45 – 50 µm. Printed inter-digitated S/D configuration (left), Microscopic image of inkjet printed metallic lines (right).
Completed two major process improvement cycles for the two critical elements of our low temperature (180°C) a-Si TFT platform. These improvements enable us to produce TFTs with acceptable yield and with performance that is equal to or superior than TFTs fabricated by major manufacturers at much higher temperature. This improvement was demonstrated with 4-in diagonal QVGA EP display panels in cooperation with E Ink.
Demonstrated Keithley Instruments SCS4200 Parameter Analyzer, Wentworth Laboratories triaxial probe card and Electroglass 2001x Wafer Prober used as a production tool to achieve comprehensive I-V TFT characterization with Current range spanning 9 orders-of-magnitude and femto-ampere sensitivity.
First 4-in. diagonal QVGA display builds were completed. The TFT array was custom-designed with E Ink for integration with their electrophoretic FPL. The maskset layout for the 6” wafer-scale toolset is shown. This maskset includes PCM structures and assorted novel circuitry for R&D.
1.1-inch 64 x 64 EP displays built on SS were demonstrated.
Integrated Column Drivers for 4-inch QVGA EP displays using a-Si TFTs on flexible SS substrates were developed. The design reduces the number of interconnects by more than 3x compared to a display with external drivers thereby reducing cost and improving reliability.
DuPont Teijin Films, a technology leader in high performance plastic substrates became an Associate Member of the FDC.
1.1-inch 64 x 64 concept devices completed: OLEDs were successfully integrated on FDC’s low temperature 1.1-in. 64 x 64 a-Si backplanes (2T per pixel) on silicon. UDC applied the OLED and glass encapsulation and Honeywell provided the integration. Cholesteric liquid crystal frontplanes were integrated with FDC backplanes by Kent Displays, and electrophoretic frontplanes were integrated in-house with technology transferred to FDC by E Ink. Images of the displays are shown.
The low temperature a-Si process was transferred to stainless steel (SS) and PEN substrates using the 1.1-inch 64 x 64 mask set and resulting in functional TFTs. Fabricated and manually debonded 1.1-inch TFT Arrays on PEN are shown to the right.
World’s first GEN II photolithography tool, Azores 5200g PanelPrinter™ with automatic substrate distortion compensation ( active compensation architecture (ACA)) specifically designed and optimized for manufacturing with flexible panels was qualified in the FDC Class 10 Clean Room. The tool development was funded by the USDC.
World’s first GEN II high material utilization efficiency (>90%) mist coater installed and qualified. This tool was co-designed and developed with FDC member EVG.
Four additional technology leaders became members of the FDC. Associate Members: Rockwell Collins, Inc., Nitto Denko Corporation, and Litrex Corporation; Technology Users : L3 Communications Corporation
The 6-in Research Level Pilot Line is qualified with fabrication of the first full-flow processed wafers. A comprehensive suite of Metrology tools was fully implemented at this time.
In collaboration with Honeywell, a 1.1-in diagonal OLED display was demonstrated using FDC designs for two transistor 64 x 64 pixel arrays (80 dpi). Honeywell fabricated reflective and emissive, 1.1-inch diagonal backplanes on heat stabilized PEN plastic substrates (Q65/Teonex TM) using one mask set designed by the FDC to produce 3 reflective and 1 emissive backplanes, as well as their own mask set to produce three emissive backplanes.
A Ribbon Cutting Ceremony officially recognizing the opening of the FDC was conducted with the U.S. Army Research Lab (ARL). Dr. Michael M. Crow, President ASU, co- hosted the event with The Honorable J.D Hayworth Arizona Congressman U.S. House of Representatives, The Honorable Claude M. Bolton Jr., Assistant 
Secretary of the Army for Acquisition, Logistics and Technology (ASA(ALT)), Dr. Thomas H. Killion, Deputy Assistant Secretary for Research and Technology and Chief Scientist (ASA(ALT)), BG(P) Roger A. Nadeau, commanding General, U.S. Army Research Development and Engineering Command/Army Acquisition Executive. Industry Speakers included: Dr. Michael Hack, VP UDC, Dr. Peter Podessor, CEO and President EV Group, and Mr. Manny Mora VP and Division Manager GD, Total attendance was ~350. Media coverage included a prime time lead news story on ABC and more than ten articles in the popular press (Army News Service, Wafer News, AZ Republic, and AZ Tribune).
Twelve companies representing leaders in their respective technologies became Charter Members of the FDC. Principal Members: Honeywell International, EV Group Inc., Universal Display Corporation (UDC), U.S. Display Consortium (USDC). Associate Members : E Ink Corporation, Kent Displays Inc., ITO America, Corning Inc. Abbie Gregg Inc., Surface Science Integration (SSI). Technology Users : General Dynamics C4 Systems and Raytheon.
A Center Member Participation Agreement (PA) incorporating the IP framework was crafted by Center management with input from AZTE, ASU legal counsel, and nine potential member companies was finalized.
A General Membership Meeting was conducted to advance company memberships, communicate start-up and technical progress, initiate the Annual Program Planning process, and to convene the Governing Board to establish member governance. Honeywell, UDC, EVG, STMicroelectronics, Kent Displays, DuPont Teijien Films, Eikos, General Dynamics, Raytheon, Northrop Grumman and Rockwell-Collins were represented. Preliminary display specifications were delivered and TAB Working Groups reported technical challenges and provided rough roadmaps.
The Center Kickoff Meeting was conducted at the FDC. Approximately seventy-five government, academic and industry representatives attended for presentations on the FDC overview, management plan, Annual Program Plan (APP), participation model, and IP framework.
The FDC was moved it to its one-of-a-kind facility originally built as Motorola’s Flat Panel Display Headquarters. The 25,000 sq. ft. facility is located in ASU Research Park, Tempe, Arizona with 43,500 sq. ft. of Class 10/1,000/10,000 Fabrication Clean Rooms and 22,000 sq. ft. of wet/dry laboratories.
ASU received a $43.7 million federal award from the Army through a Cooperative Agreement to begin developing revolutionary compact, lightweight, ultra-rugged, low-power information displays.